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NEW QUESTION: 1
회사는 RDS MySQL 인스턴스에서 실행되는 주 트랜잭션 DB에서 매시간 배치 분석을 실행하여 Redshift에서 실행되는 중앙 데이터웨어 하우스를 채 웁니다. 배치를 실행하는 동안 트랜잭션 응용 프로그램은 매우 느립니다. 배치가 완료되면 최고 관리 대시 보드를 새 데이터로 업데이트해야합니다. 대시 보드는 수동으로 보낸 전자 메일에서 업데이트가 필요하다고 알릴 때 현재 시작되는 온 - 프레미스를 실행하는 다른 시스템에서 생성됩니다. 다른 팀에서 관리하므로 온 - 프레미스 시스템을 수정할 수 없습니다. 성능 문제를 해결하고 가능한 한 프로세스를 자동화하기 위해이 시나리오를 어떻게 최적화 하시겠습니까?
A. 일괄 처리 분석을 위해 RDS 읽기 복제본을 만들고 사내 시스템에 대시 보드를 업데이트하도록 알리는 SNS를 만듭니다.
B. 일괄 처리 분석을 위해 RDS를 Redshift로 대체하고 SNS를 사용하여 구내 시스템에 대시 보드를 업데이트하도록 알립니다.
C. 일괄 처리 분석을 위해 RDS를 Redshift로 대체하고 SQS를 사용하여 사내 구축 형 시스템으로 메시지를 보내 대시 보드를 업데이트합니다
D. 배치 분석을 위해 RDS 읽기 복제본을 만들고 사내 구축 형 시스템에 메시지를 보내 SQS가 대시 보드를 업데이트합니다.
Answer: A

NEW QUESTION: 2
Refer to the exhibit.

An administrator manages a wireless network in a building. Which default gateway must be given to the users through DHCP in order for them to access resources throughout the building?
A. 3 - Router in the data center
B. 1 - Aruba AP on that respective floor
C. 2 - Switch on that respective floor
D. 4 - Aruba Mobility Controller in the data center
Answer: A

NEW QUESTION: 3

Refer the exhibit. Which of the following is the correct output of the above executed command? A)

B)

C)

D)

A. Option D
B. Option A
C. Option B
D. Option C
Answer: D

NEW QUESTION: 4
The design of the z13 Systems processor unit (PU) chip has been enhanced over the zEC12.
Which of the following characterizes the improvement?
A. Larger cache level sizes on z13 compared to zEC12.
B. Up to six active cores per chip on z13 compared to four active cores on zEC12.
C. Faster processor cycle time on z13 (5.5 GHz instead of 5.0 GHz on zEC12).
D. Improved cryptographic and compression engine shared over all cores.
Answer: A
Explanation:
Contributing to the additional capacity on the z13 and z13s are numerous improvements in processor chip design, including new instructions, multithreading, and redesigned and larger caches.
Z13 processor:
* L1 cache
9 6 KB I-L1
1 28 KB D-L1 per core
* L2 cache
2 MB I-L2
2 MB D-L2 per core
L3 cache 64 MB shared
zEC12 processor:
L1 cache64+96 KB/core
L2 cache1+1 MB/core
L3 cache48 MB/chip
References:
https://en.wikipedia.org/wiki/IBM_zEC12_(microprocessor)
https://en.wikipedia.org/wiki/IBM_z13_(microprocessor)